Registry / data / pyvcd
library0.4.1pypypi✓ verified 85d ago

pyvcd is a Python library designed for working with Value Change Dump (VCD) files. It provides functionalities for both reading and writing these standard files used to record signal activity in digital logic simulations. The current version is 0.4.1, and releases are generally made on an as-needed basis for bug fixes or minor enhancements.

pip install pyvcd
INSTALL
IMPORT
SIG · PYVCD
P
pyvcd
datapythonv0.4.1
Install
1.5s avg
Import
Disk
16MB
Pass rate
10/ 10
Env Coverage10 / 10
glibc
3.93.13
musl
3.93.13
Install & Compatibility
Where this runs
tested against v0.4.1 · pip install
no network on importno background threads
Install × environment matrix
Each cell = how many times install + import succeeded across repeated harness runs. Partial = flaky.
glibc = Debian/Ubuntu slim · musl = Alpine Linux
musl
py 3.103.910 runs
installs and imports cleanly · install 0.0s · import 0.000s · 17.9MB
glibc
py 3.103.910 runs
installs and imports cleanly · install 1.5s · import 0.000s · 18MB
16MB installed
● package 16MB
Code
Verified usage

Verified import paths — ran on the pinned version, not inferred.

VCDWriter
from vcd import VCDWriter
from pyvcd import VCDWriter
VCDPhaseError
from vcd import VCDPhaseError
reader
from vcd import reader

This example demonstrates how to create a VCD file, define a module scope, declare signals (wires), and record their value changes over time using `VCDWriter`.

from datetime import datetime from pyvcd import VCDWriter # Create a VCD file named 'test.vcd' with VCDWriter(open('test.vcd', 'w'), timescale='1 ns', date=datetime.now()) as writer: # Enter a scope named 'top' of type 'module' scope = writer.scope_stack.enter_scope('top', 'module') # Define a 1-bit 'clk' wire and change its value over time writer.change(scope.var('clk', 'wire', 1), 0, 0) # At time 0, clk is 0 writer.change(scope.var('clk', 'wire', 1), 1, 100) # At time 100 ns, clk is 1 writer.change(scope.var('clk', 'wire', 1), 0, 200) # At time 200 ns, clk is 0 # Define another 1-bit 'rst_n' wire writer.change(scope.var('rst_n', 'wire', 1), 1, 0) writer.change(scope.var('rst_n', 'wire', 1), 0, 100) writer.change(scope.var('rst_n', 'wire', 1), 1, 200) # Leave the current scope writer.scope_stack.leave_scope() print("VCD file 'test.vcd' generated successfully.")
Debug
Known issues
gotchaForgetting to use `VCDWriter` in a `with` statement or manually `close()` the writer can lead to incomplete or corrupted VCD files, as internal buffers might not be flushed to disk.
fix
Always use `VCDWriter` as a context manager: `with VCDWriter(open('file.vcd', 'w'), ...) as writer:`
affects: All
gotchaThe `timescale` argument to `VCDWriter` is crucial for the correct interpretation of timestamps by VCD viewers. Missetting it (e.g., '1ps' when the simulation operates in '1ns' increments) will result in incorrect timing displays.
fix
Ensure `timescale` (e.g., '1 ns', '1 ps', '1 us') accurately reflects the time units used for your simulation data.
affects: All
gotchaSignal values are expected to be integers for `wire` types by default. Providing non-integer values without proper conversion can lead to `TypeError` or `ValueError` or incorrect data representation in the VCD file.
fix
Ensure values passed to `writer.change()` for `wire` types are integers. For bit-string representations, consider converting to integer or ensuring your VCD viewer handles them correctly.
affects: All
Upgrade
Version history
0.4.1latest on PyPI · released Nov 10, 2024
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Agent activity
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Resources
pyvcd — pip install pyvcd · libregistry