PeakRDL-regblock is a free and open-source control & status register (CSR) compiler. It translates SystemRDL register descriptions into synthesizable SystemVerilog RTL modules for hardware designs. The library is actively maintained, with a recent major release (1.0.0) in April 2025, and subsequent minor releases, currently at version 1.3.1, indicating a rapid release cadence.
pip install peakrdl-regblockVerified import paths — ran on the pinned version, not inferred.
This quickstart demonstrates how to programmatically compile a simple SystemRDL description and then export it into a SystemVerilog register block using the `RegblockExporter`. It specifies an AXI4-Lite CPU interface and outputs the generated files to a directory named 'generated_regblock'. Alternatively, the primary method for most users is via the `peakrdl regblock` command-line tool.
Upgrade Python environment to 3.7+.
Always access `hwif` struct members directly by name (e.g., `hwif_out.my_reg.my_field.value`) to ensure correct behavior and avoid assumptions about bit-positions.
For VHDL, install `peakrdl-regblock-vhdl` (e.g., `pip install peakrdl-regblock-vhdl[cli]`) and use its corresponding tools/APIs.
Avoid using the `alias` keyword in your SystemRDL descriptions. Restructure your register definitions to avoid this feature.
Install `peakrdl-regblock` with the `[cli]` extra: `pip install peakrdl-regblock[cli]`. If `peakrdl` is desired as a standalone, ensure it is also installed (`pip install peakrdl`).
Carefully review the SystemRDL code against the SystemRDL 2.0 specification for correctness. Use a linter or an RDL editor if available.
Ensure you are passing an appropriate CPU interface class (e.g., `cpuif_cls=AXI4Lite` from `peakrdl_regblock.cpuif`) to the `exporter.export()` method. The `node` argument should be the compiled `RootNode` or `AddrmapNode` of your register block.